Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDS), or in any other type of memory cell.
Other types of PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDS are known as mask programmable devices. PLDS can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
Each new generation of chip technology allows additional functionality to be integrated on a single chip. Functions that were once implemented on several chips can now be integrated on a single chip. There are numerous applications in which entire systems are implemented on a single chip (“system on a chip”). In one application, a general purpose processor may be embedded within PLD circuitry.
In order to manufacture a chip with a processor embedded in PLD circuitry, an overall circuit design of the combined circuitry must be prepared. Part of this overall design may involve special interface circuitry that connects the processor input/output (I/O) pins to desired pins in the PLD circuitry. A processor may have many interface pins, perhaps thousands, which complicates the task of designing the interface.
The challenges associated with coordinating the many pin-to-pin connections arise in the different design views that are used at different times in the design process. For example, one view provides information for routing signals between the processor pins and PLD pins along with setting necessary default values; another view provides a schematic representation that may be used to view signal routes; another view includes the physical coordinates of pins in a placed and routed circuit; and another view provides test information for testing behavior of the circuit.
The information used to prepare these views may come from different groups having different responsibilities in preparing the overall circuit design. Coordinating pin definitions between the different groups, however, may be difficult. Consistency of pin definitions and connections between the different design views is critical for the circuit to operate correctly. Furthermore, changes in either the processor design or the design of the PLD circuitry may change the needed connections between the I/O pins of the processor and pins in the PLD circuitry. Thus, embedding a new version of a processor in the PLD circuitry may involve a significant amount of work in updating the interface design and ensuring consistency between the different design views.
The present invention may address one or more of the above issues.